Ritesh Yadav
Building high-throughput GPU kernels, enterprise Agentic AI systems, and cloud-native LLMOps infrastructure.
I am an AI/ML Engineer working across the full spectrum of machine learning engineering: from writing custom CUDA SGEMM kernels and optimizing hardware memory hierarchies to orchestrating enterprise multi-agent systems with LangGraph, Model Context Protocol (MCP), and scaling cloud-native Kubernetes platforms.
Currently at 66degrees, I architect multi-horizon time-series forecasting engines (TFT and TiDE across 141 configurations on Vertex AI and GKE) and multi-agent extraction systems with LangGraph supervisors, human-in-the-loop gates, and LiteLLM telemetry. Previously at IntellectAI, I scaled financial GenAI platforms to sub-200ms p95 latency, integrated automated LLM-as-a-judge evaluation harnesses, and deployed serverless inference pods with cold-start pre-warming.
Core Engineering Pillars & Technology Stack
Production ExpertiseAgentic AI & Multi-Agent Orchestration
Autonomous Agent Supervision, Tool Protocols & Reasoning
Advanced RAG, Vector Search & Enterprise Graph
Hybrid Retrieval, Knowledge Graphs & Semantic Memory
LLMOps, AI Security & Enterprise Governance
Automated Evaluation, Observability, Guardrails & Access Control
GPU Kernels, Cloud MLOps & Kubernetes Platform
Custom Compute Kernels, Serverless GPU Serving & Infrastructure
Inside the Blackwell SM: How NVIDIA Redesigned the Building Block of GPU Computing
A plain-English walkthrough of the NVIDIA Blackwell Streaming Multiprocessor: TMA asynchronous bulk transfers, 5th Generation Tensor Cores (tcgen05), 128-lane TMEM accumulators, and how they pipeline GEMM at peak speed with zero register spill penalties. Includes 4 standalone retro hardware schematics.
Research Topics & Glossary Roadmap
6 Core AreasThis is the primary map of the research notes. Each card links directly to its category overview, architectural notes, and kernels.
Device Hardware
Streaming Multiprocessor internals, HBM3e memory hierarchy, TMA asynchronous engines, and dedicated TMEM accumulators.
Device Software
CUDA kernel programming, 1D and 2D block tiling, 128-bit vectorized float4 memory loads, and warp execution models.
Host Software
Driver APIs, CUDA runtime architecture, CUTLASS primitives, and CuTe tensor layout abstractions.
Performance Profiling
Roofline analysis, arithmetic intensity, memory coalescing, and eliminating 32-way shared memory bank conflicts.
Inference Engineering
Low-latency LLM serving, FP8 and FP4 quantization, speculative decoding, and production serving engines like vLLM.
Large Language Models
Attention kernels, FlashAttention mechanisms, Mixture-of-Experts routing, and distributed tensor parallelism.
Research Syllabus & Coverage Table
Reference MapComplete structural map of the glossary notes detailing the scope and microarchitectural questions each research area is designed to address.
| # | Research Area | What It Covers | Access |
|---|---|---|---|
| 01 | Device Hardware | Streaming Multiprocessor internals, HBM3e memory hierarchy, TMA asynchronous engines, and dedicated TMEM accumulators. | Browse → |
| 02 | Device Software | CUDA kernel programming, 1D and 2D block tiling, 128-bit vectorized float4 memory loads, and warp execution models. | Browse → |
| 03 | Host Software | Driver APIs, CUDA runtime architecture, CUTLASS primitives, and CuTe tensor layout abstractions. | Browse → |
| 04 | Performance Profiling | Roofline analysis, arithmetic intensity, memory coalescing, and eliminating 32-way shared memory bank conflicts. | Browse → |
| 05 | Inference Engineering | Low-latency LLM serving, FP8 and FP4 quantization, speculative decoding, and production serving engines like vLLM. | Browse → |
| 06 | Large Language Models | Attention kernels, FlashAttention mechanisms, Mixture-of-Experts routing, and distributed tensor parallelism. | Browse → |